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₹1.27 Lakh Crore Semicon 2.0 Notified: Boosts Domestic Chip Design, Manufacturing, and R&D

Target:UPSC GS-IIIMPSCSSC GATeachingPrelims HighMains HighStatic GK Link
31 Aug 2026
~2 min
Source: Indian Express
Key Data:₹1.27 lakh crore40% capex for fabs35% for advanced packaging30% for supply chain units₹15 crore seed funding5% royalty revenue
Bodies:C-DACMinistry of Electronics and Information TechnologyTata ElectronicsMicron TechnologyPSMC
Practice MCQs from today's news ▸
What This Article Covers

1.Semicon 2.0, with ₹1.27 lakh crore outlay, expands semiconductor strategy to six pillars covering chip design, manufacturing, packaging, and supply chain.

2.Three pillars dedicated to chip design: strategic chips, commercial fabless companies, and domestically deployed chips. C-DAC to oversee strategic IP development.

3.Incentives include seed funding up to ₹15 crore for startups, royalty financing, capex support of 30-40% for fabs, and production-linked incentive for equipment manufacturers.

The Big Picture
Prelims · HighMains · High

The government notified the operational framework for Semicon 2.0, a ₹1.27 lakh crore program to boost domestic chip design, manufacturing, and supply chain. It includes six pillars, with incentives for chip design, fabrication plants, packaging, and R&D. This is critical for India's semiconductor ecosystem and self-reliance.

Exam Lens

Quick Exam Facts From News

Total Outlay₹1.27 lakh crore
Capex Support for Fabs40% (silicon wafer fabs, min ₹20,000 crore investment)
Seed Funding for StartupsUp to ₹15 crore or 50% of project cost
Capex Support for Packaging35% (advanced), 25% (legacy)
Target Engineers1 lakh more (85,000 achieved in 4 years)
Plants Approved under ISM 1.012 chip plants

1-Minute Revision

  • ›Total Outlay: ₹1.27 lakh crore
  • ›Capex Support for Fabs: 40% (silicon wafer fabs, min ₹20,000 crore investment)
  • ›Target this Data: ₹1.27 lakh crore outlay for Semicon 2.0
  • ›Target this Nodal Body: Ministry of Electronics and Information Technology (MeitY) and C-DAC
  • ›Target this Legal Point: Six pillars of Semicon 2.0 including chip design, manufacturing, packaging, supply chain

Mastered this topic? Test your knowledge with a full MCQ quiz.

Practice exam-style questions, track your score, and strengthen your recall.

Q1Static LinkageEasy

Which ministry is primarily responsible for implementing the Semicon 2.0 programme?

Q2Statement-basedHard

Consider the following statements:

1. Semicon 2.0 has a total outlay of ₹1.27 lakh crore.

2. The programme provides capital expenditure support of 40% for advanced semiconductor packaging.

3. C-DAC will issue requests for proposals for strategic chip design.

Which of the statements given above is/are correct?

Q3Data-centricMedium

What is the seed funding limit for startups designing commercial chips under Semicon 2.0?

Q4Application/ImpactMedium

What is the primary objective of the Semicon 2.0 programme?

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